An integrated circuit is fabricated by translating a circuit design or layout to a semiconductor substrate. In optical lithography, the layout is first transferred onto a physical template, which is in turn, used to optically project the layout onto a silicon wafer. In transferring the layout to a physical template, a mask is generally created for each layer of the integrated circuit design. To fabricate a particular layer of the design, the corresponding mask is placed over the wafer and light is shone through the mask from the energy source. The end result is a semiconductor wafer coated with a photoresist layer having the desired pattern that defines the geometries, features, lines and shapes of that layer. The photolithography process is typically followed by an etch process during which the underlying substrate not covered or masked by the photoresist pattern is etched away, leaving the desired pattern in the substrate. This process is then repeated for each layer of the design.
Referring now to FIG. 1, a portion of a desired semiconductor pattern and the patterned layer resulting from the masking process is shown. The semiconductor pattern shown in dashed lines includes various pattern elements 102a, and 102b (collectively referred to as pattern elements 102). Using the pattern, a masking process is used to create the patterned layer 131, comprising the actual elements 132. The patterned layer 131 may comprise, in alternative embodiments, a photoresist pattern produced by a photolithography process or a substrate pattern produced by an etch process.
As will be appreciated to those skilled in the art of semiconductor processing and design, elements 102 of semiconductor pattern includes various interconnect sections and pattern elements designed to achieve a desired function when the integrated circuit contemplated by the semiconductor fabrication process is completed. Typical elements 102 of a semiconductor pattern are substantially comprised of straight lines and square corners. For a variety of reasons, reproducing the exact image of semiconductor pattern in a production process is extremely complicated due to the large number of parameters associated with typical masking processes and further due to the unavoidable diffraction effects which inevitably result in some variations between the photomask used to produce a pattern and the pattern itself.
It is seen in FIG. 1 that the actual pattern 131 produced by a masking process varies from the desired semiconductor pattern 102. This discrepancy is shown in FIG. 1 as the displacement between the dashed lines of pattern elements 102a and 102b and the actual pattern elements 132a and 132b. Typically, the variations from the idealized pattern 102 include rounding of the corners and a shrinking of the line widths. It will be appreciated to those skilled in the art of semiconductor processing that variations from the desired semiconductor pattern can contribute to lower processing yields, reduced reliability, reduced tolerance to subsequent misalignment, and other undesired effects.
To analyze the pattern on the wafer, or the mask used to create the pattern, a scanning electron microscope (SEM) may be used to create a digital image of the wafer or mask. An SEM image is typically a gray-scale raster image, where each pixel position includes an integer value between 0 and 255 representing brightness or intensity. The patterned elements or features in the SEM image may have the same or different brightness levels as the background of the image, but the edges of the features appear as lines having different brightness levels than the internal feature areas and the background.
The use of SEM images has many applications in the field of masking process simulation. Masking process simulation software is commercially available that is capable of producing a simulated estimate of the pattern that would be produced by a specified masking process using a given photomask. Examples of process simulation software include TSUPREM-4™ and Taurus-LRC™ by Synopsys, Inc. of Mountain View, Calif. Masking process simulators are useful for generating a large quantity of information concerning the effects of modifying various parameters associated with the process.
Although simulation software is used to avoid the time and expense associated with producing actual test wafers, the simulator's estimate of the pattern, referred to as an aerial or latent image, usually varies from the actual pattern produced by the masking process (due to diffraction effects and variations in the masking process) regardless of the number of parameters incorporated into the simulator.
The Assignee of the present application has developed a process that improves the process simulator's prediction of the final pattern produced by a masking process by using the actual results generated by the masking process. For example, U.S. patent application Ser. No. 10/305,673, entitled “Automatic Calibration Of A Masking Process Simulator” (2631P) filed on Oct. 22, 2002. discloses a process that introduces a feedback mechanism into the simulation process whereby the discrepancies observed between the actual pattern and the aerial image are analyzed to produce a calibrated simulator that results in less discrepancy, or error between the aerial image produced during a successive iteration of the simulator and the actual image produced by the pattern.
The discrepancies between the actual pattern and the aerial image are observed by obtaining an SEM image of the pattern from a wafer, detecting the edges of the patterned features in the image, and comparing the detected edges to the aerial image. The simulator is then modified until it produces an aerial image that matches the detected edges with a minimum amount of error. Of course, the method used to detect or recognize the edges of the features of the SEM image is of utmost importance to ensuring the accuracy of the calibration process.
Accurate recognition of edges is usually implemented as a two-stage procedure: during the first stage, one has to find approximate locations of edges, and the second stage involves refining these locations. Stage one sometimes allows significant location errors (for example, up to 5 or 10 pixels), but the topology as a whole (i.e., set of separate edges with their mutual positions) must be detected without errors: edges must be continuous lines, without holes, no one edge can be lost, two separate edges cannot be merged, and so on.
Accordingly, what is needed is a more accurate method for finding the approximate locations of the edges in an SEM image during the first stage of edge recognition. The present invention addresses such a need.